There are multiple ways to achieve what you want. Here I describe a way to record the time instants of the clock edges into a file during the XMODEL simulation.

Shown below is the schematic of the sandbox.tb_record_clk:schematic cellview included in the attached package. A 'clk_gen' primitive produces a noisy clock signal 'clk'. And to record its timing instants into a text file, three XMODEL primitives are used: 'trig_posedge', 'meas_time', and 'inline' primitives. First, the 'trig_posedge' primitive produces a trigger signal 'trig', which is triggered whenever the positive edge of 'clk' occurs. Second, the 'meas_time' primitive outputs the real-type time value 'tval' indicating when the 'trig' signal is triggered. Third, the 'inline' primitive records this time value into a file.

An 'inline' primitive lets you add SystemVerilog codes to your schematic testbench or model. In this example, the 'inline' primitive contains the following codes, which opens a file named "timing.dat" at the beginning of a simulation, records the input time value to the file whenever it is updated during the simulation, and closes the file at the end of the simulation.

Here is the content of the file "timing.dat" produced after running the simulation. As expected, it lists the time instant values of all the positive edges of the clock.

And here is a simple Python script example that can read this file and compute the statistics of the clock's period jitter. This script is included in the attached package as 'bin/calc_pj.py' file.

#!/usr/bin/env xmodelpy

import numpy as np

t_clk = np.loadtxt('timing.dat')
periods = t_clk[1:] - t_clk[:-1]
print "AVERAGE PERIOD    = %e" % periods.mean()
print "RMS PERIOD JITTER = %e" % periods.std()
print "PP PERIOD JITTER  = %e" % periods.ptp()

As an additional note, the testbench shown above can be modified in various ways to make different measurements. For example, one can use a 'trig_negedge' or 'trig_edge' primitive instead of the 'trig_posedge' primitive to record the time instants of the negative edges or both the edges, respectively. Also, note that one can use a 'meas_posedge' primitive instead of the combination of 'trig_posedge' and 'meas_time' primitives for making the same measurements.

Attachment: record_clk_20220503.tar.gz

The XMODEL 2022.10 Release introduces a new 'probe_value' primitive, which can measure the values of an xreal-type input signal at specified trigger events and record the results to a text file. For the above example, this 'probe_value' primitive can replace the 'inline' primitive containing the Verilog code, as shown below.

Below is the content of the text file named "probe_value.dat" produced after the simulation:

Compared to the "timing.dat" file produced in the above example, this "probe_value.dat" file starts with a header line (#DATAFILE …) and a dummy value '-nan'. This dummy value is printed because at the very first triggering event, the 'meas_time' primitive hasn't made any measurements yet and produces no valid output. While one way to avoid this dummy value is to delay the trigger signal 'trig' before it drives the 'probe_value' primitive, a simpler way is to just ignore the first two lines when reading the text file using the 'skiprows' argument of the numpy.loadtxt() function. Here is an example of showing how to do it.

#!/usr/bin/env xmodelpy

import numpy as np

t_clk = np.loadtxt('probe_value.dat', skiprows=2)
periods = t_clk[1:] - t_clk[:-1]
print "AVERAGE PERIOD    = %e" % periods.mean()
print "RMS PERIOD JITTER = %e" % periods.std()
print "PP PERIOD JITTER  = %e" % periods.ptp()

There are multiple ways to achieve what you want. Here I describe a way to record the time instants of the clock edges into a file during the XMODEL simulation.

Shown below is the schematic of the sandbox.tb_record_clk:schematic cellview included in the attached package. A 'clk_gen' primitive produces a noisy clock signal 'clk'. And to record its timing instants into a text file, three XMODEL primitives are used: 'trig_posedge', 'meas_time', and 'inline' primitives. First, the 'trig_posedge' primitive produces a trigger signal 'trig', which is triggered whenever the positive edge of 'clk' occurs. Second, the 'meas_time' primitive outputs the real-type time value 'tval' indicating when the 'trig' signal is triggered. Third, the 'inline' primitive records this time value into a file.

An 'inline' primitive lets you add SystemVerilog codes to your schematic testbench or model. In this example, the 'inline' primitive contains the following codes, which opens a file named "timing.dat" at the beginning of a simulation, records the input time value to the file whenever it is updated during the simulation, and closes the file at the end of the simulation.

Here is the content of the file "timing.dat" produced after running the simulation. As expected, it lists the time instant values of all the positive edges of the clock.

And here is a simple Python script example that can read this file and compute the statistics of the clock's period jitter. This script is included in the attached package as 'bin/calc_pj.py' file.

#!/usr/bin/env xmodelpy

import numpy as np

t_clk = np.loadtxt('timing.dat')
periods = t_clk[1:] - t_clk[:-1]
print "AVERAGE PERIOD    = %e" % periods.mean()
print "RMS PERIOD JITTER = %e" % periods.std()
print "PP PERIOD JITTER  = %e" % periods.ptp()

As an additional note, the testbench shown above can be modified in various ways to make different measurements. For example, one can use a 'trig_negedge' or 'trig_edge' primitive instead of the 'trig_posedge' primitive to record the time instants of the negative edges or both the edges, respectively. Also, note that one can use a 'meas_posedge' primitive instead of the combination of 'trig_posedge' and 'meas_time' primitives for making the same measurements.

Attachment: record_clk_20220503.tar.gz

The XMODEL 2022.10 Release introduces a new 'probe_value' primitive, which can measure the values of an xreal-type input signal at specified trigger events and record the results to a text file. For the above example, this 'probe_value' primitive can replace the 'inline' primitive containing the Verilog code, as shown below.

Below is the content of the text file named "probe_value.dat" produced after the simulation:

Compared to the "timing.dat" file produced in the above example, this "probe_value.dat" file starts with a header line (#DATAFILE …) and a dummy value '-nan'. This dummy value is printed because at the very first triggering event, the 'meas_time' primitive hasn't made any measurements yet and produces no valid output. While one way to avoid this dummy value is to delay the trigger signal 'trig' before it drives the 'probe_value' primitive, a simpler way is to just ignore the first two lines when reading the text file using the 'skiprows' argument of the numpy.loadtxt() function. Here is an example of showing how to do it.

#!/usr/bin/env xmodelpy

import numpy as np

t_clk = np.loadtxt('probe_value.dat', skiprows=2)
periods = t_clk[1:] - t_clk[:-1]
print "AVERAGE PERIOD    = %e" % periods.mean()
print "RMS PERIOD JITTER = %e" % periods.std()
print "PP PERIOD JITTER  = %e" % periods.ptp()