Sure. Here is a simple way of modeling a duty-cycle adjuster (DCA) circuit you described. The screenshot below is the model schematic of a cellview named sandbox.dca_n:schematic included in the attached package. It adjusts the duty-cycle of the input clock arriving at 'in' by varying its rising-edge delay or falling-edge delay to the output 'out'. The amount of duty-cycle adjustment is controlled by another input signal 'vc'.

The key idea is to first convert the input digital signal (in) to an analog signal with finite rise and fall times (in_slew) and then slice it at the threshold level set by the control input (vc) to produce the output digital signal (out). For example, when vc increases, the rising-edge delay from in to out increases but the falling-edge delay decreases, and as a result, the duty-cycle of the clock signal shrinks. The amount of change in the delays and hence the duty-cycle with respect to a unit change in vc is set by the finite rise time and fall time of in_slew.

The example model defines four parameters: Kd_r, Kd_f, vc_max, and vc_min. The parameters vc_max and vc_min define the maximum and minimum values of the control input vc, respectively. That is, the DCA model makes no further change to the duty-cycle when vc is outside the range of vc_min~vc_max. The parameters Kd_r and Kd_f define the gain or sensitivity of the rising-edge delay and falling-edge delay with respect to the change in vc, respectively. In this DCA model, the rising-edge delay increases and falling-edge delay decreases as vc increases. We will see later how to model a DCA with the opposite behavior.

The DCA model 'dca_n' shown above consists of three XMODEL primitives: transition, slice, and limit. The 'transition' primitive converts the digital input 'in' to an analog signal 'in_slew' with a rise time of Kd_r*(vc_max-vc_min) and fall time of Kd_f*(vc_max-vc_min), and with a logic-0 level at vc_min and logic-1 level at vc_max. And the 'slice' primitive converts 'in_slew' to the digital output 'out' by comparing it with the threshold level vc_limit. The 'limit' primitive makes sure that this threshold level vc_limit derived from vc is neither greater than vc_max nor less than vc_min. In fact, to allow the clock signal to propagate from in to out even when vc is equal to vc_min or vc_max, the logic-0 and logic-1 levels of the 'transition' primitive are padded with 0.1% margin.

Let's check the operation of this model using a testbench shown below. It is feeding a 200MHz clock to the input 'in' and a gradually varying signal from 0.0 to 1.0V to the input 'vc'. The assumed model parameters are Kd_r=1n, Kd_f=1n, vc_max=1.0 and vc_min=0.0.

Here are the simulated waveforms of the signals in, in_slew, vc, and out. As expected, as vc increases, the rising-edge delay increases but the fall-edge delay decreases, and as a result, the duty-cycle of the output clock decreases.

Some DCA circuits adjust only the rising-edge delay or falling-edge delay, but not both. Here are the simulated waveforms of a DCA adjusting only the rising-edge delay, for example, by setting Kd_r=2n and Kd_f=0.0. In this case, only the rising-edge delay increases as vc increases while the falling-edge delay is fixed. On the other hand, we can easily guess the operation when only the falling-edge delay is made adjustable (e.g. Kd_r=0.0 and Kd_f=2n).

Now, how do we model a DCA circuit of which output duty-cycle increases with vc? The easiest way to extend what we described so far is to add inverters at the input and output of the previous 'dca_n' model. We named this model 'dca_p' in the attached package and its schematic is shown below.

And the simulated waveforms shown below confirm that the duty-cycle of its output indeed increases as vc increases.

The attached package contains the models and testbench described in this posting. Please follow the steps outlined below to source the setup.bashrc or setup.cshrc file and launch Cadence Virtuoso.

$ tar zxvf dca_20220222.tar.gz
$ cd dca
$ source etc/setup.bashrc      # for bash shells
$ source etc/setup.cshrc       # for csh-like shells
$ cd cadence
$ virtuoso &

Attachment: dca_20220326.tar.gz

Sure. Here is a simple way of modeling a duty-cycle adjuster (DCA) circuit you described. The screenshot below is the model schematic of a cellview named sandbox.dca_n:schematic included in the attached package. It adjusts the duty-cycle of the input clock arriving at 'in' by varying its rising-edge delay or falling-edge delay to the output 'out'. The amount of duty-cycle adjustment is controlled by another input signal 'vc'.

The key idea is to first convert the input digital signal (in) to an analog signal with finite rise and fall times (in_slew) and then slice it at the threshold level set by the control input (vc) to produce the output digital signal (out). For example, when vc increases, the rising-edge delay from in to out increases but the falling-edge delay decreases, and as a result, the duty-cycle of the clock signal shrinks. The amount of change in the delays and hence the duty-cycle with respect to a unit change in vc is set by the finite rise time and fall time of in_slew.

The example model defines four parameters: Kd_r, Kd_f, vc_max, and vc_min. The parameters vc_max and vc_min define the maximum and minimum values of the control input vc, respectively. That is, the DCA model makes no further change to the duty-cycle when vc is outside the range of vc_min~vc_max. The parameters Kd_r and Kd_f define the gain or sensitivity of the rising-edge delay and falling-edge delay with respect to the change in vc, respectively. In this DCA model, the rising-edge delay increases and falling-edge delay decreases as vc increases. We will see later how to model a DCA with the opposite behavior.

The DCA model 'dca_n' shown above consists of three XMODEL primitives: transition, slice, and limit. The 'transition' primitive converts the digital input 'in' to an analog signal 'in_slew' with a rise time of Kd_r*(vc_max-vc_min) and fall time of Kd_f*(vc_max-vc_min), and with a logic-0 level at vc_min and logic-1 level at vc_max. And the 'slice' primitive converts 'in_slew' to the digital output 'out' by comparing it with the threshold level vc_limit. The 'limit' primitive makes sure that this threshold level vc_limit derived from vc is neither greater than vc_max nor less than vc_min. In fact, to allow the clock signal to propagate from in to out even when vc is equal to vc_min or vc_max, the logic-0 and logic-1 levels of the 'transition' primitive are padded with 0.1% margin.

Let's check the operation of this model using a testbench shown below. It is feeding a 200MHz clock to the input 'in' and a gradually varying signal from 0.0 to 1.0V to the input 'vc'. The assumed model parameters are Kd_r=1n, Kd_f=1n, vc_max=1.0 and vc_min=0.0.

Here are the simulated waveforms of the signals in, in_slew, vc, and out. As expected, as vc increases, the rising-edge delay increases but the fall-edge delay decreases, and as a result, the duty-cycle of the output clock decreases.

Some DCA circuits adjust only the rising-edge delay or falling-edge delay, but not both. Here are the simulated waveforms of a DCA adjusting only the rising-edge delay, for example, by setting Kd_r=2n and Kd_f=0.0. In this case, only the rising-edge delay increases as vc increases while the falling-edge delay is fixed. On the other hand, we can easily guess the operation when only the falling-edge delay is made adjustable (e.g. Kd_r=0.0 and Kd_f=2n).

Now, how do we model a DCA circuit of which output duty-cycle increases with vc? The easiest way to extend what we described so far is to add inverters at the input and output of the previous 'dca_n' model. We named this model 'dca_p' in the attached package and its schematic is shown below.

And the simulated waveforms shown below confirm that the duty-cycle of its output indeed increases as vc increases.

The attached package contains the models and testbench described in this posting. Please follow the steps outlined below to source the setup.bashrc or setup.cshrc file and launch Cadence Virtuoso.

$ tar zxvf dca_20220222.tar.gz
$ cd dca
$ source etc/setup.bashrc      # for bash shells
$ source etc/setup.cshrc       # for csh-like shells
$ cd cadence
$ virtuoso &

Attachment: dca_20220326.tar.gz