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A power-on reset (POR) circuit asserts a reset signal whenever the supply voltage drops below a preset threshold (VPOR) and keeps it asserted until the supply voltage has risen above the preset threshold for a minimum period of time (TPOR). How can I model this circuit in XMODEL?
A POR circuit is a small but non-trivial circuit to design in practice. However, its ideal functionality can be modeled using just a few XMODEL primitives as shown below. The first 'slice' primitive detects whether the supply voltage 'Vsup' is higher or lower than the preset threshold 'Vpor'. However, its raw output, labeled as 'a', cannot be the final output of the POR circuit. Assuming an active-low output of the POR circuit named 'RSTb', the 'RSTb' signal must switch to 0 as soon as 'Vsup' falls below 'Vpor', but can switch back to 1 only after 'Vsup' stays above 'Vpor' for the minimum reset period of 'Tpor'.
The following 'transition' primitive and second 'slice' primitive realize this asymmetric behavior. Basically, they model an inertial delay equal to 'Tpor' when propagating the rising edge of 'a' to 'RSTb', but zero delay when propagating the falling edge. The way we model these unequal rising and falling delays is identical to the one explained in this Q&A posting. The 'transition' primitive has its rising transition time set to '2*Tpor' and its falling transition time set to 0. By slicing the resulting output 'b' at its mid-level, we can obtain the desired active-low reset signal 'RSTb'.
The testbench shown below (tb_por1) checks the basic functionality of this POR model, assuming 'Vpor' of 2.0V and 'Tpor' of 100ns. It applies a supply voltage 'Vsup' that gradually increases from 0 to 2.5V and decreases from 2.5V back to 0 using a 'pwl_gen' primitive.
The simulated waveforms are shown below. As expected, the 'RSTb' output transitions from 0 to 1 when 'Vsup' stays above 2.0V for 100ns. On the other hand, 'RSTb' transitions back to 0 as soon as 'Vsup' falls below 2.0V. The waveforms of the signals 'a' and 'b' illustrate the operation of our POR model.
In practice, the design of POR circuit requires high attention to detail, as the circuit must operate robustly even in presence of supply noise. In other words, it must generate a valid reset for the required period when the supply voltage truly rises above the threshold; otherwise, it must not generate a false reset.
To see if our POR model still operates correctly in presence of supply noise, the testbench shown below (tb_por2) adds a 10MHz, 0.1V sinusoidal disturbance to the previous 'Vsup' waveform.
The simulated waveforms of the POR model in this case are shown below. Despite the presence of additional disturbance causing the instantaneous value of 'Vsup' to cross the threshold level multiple times, our POR model does not produce any glitches and de-asserts 'RSTb' only when 'Vsup' stays above 'Vpor' for the period of 'Tpor'.
Attachment: por_20220223.tar.gz
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파워-온 리셋(power-on reset; POR) 회로는 전원전압이 정해진 기준전압(VPOR) 이하로 떨어지면 바로 리셋 신호를 발생시키고, 전원전압이 다시 그 기준전압 이상에 도달하고 그 상태를 정해진 최소 시간(TPOR) 동안 유지한 후에야 리셋 신호를 끄는 회로입니다. 이러한 동작을 하는 POR 회로를 XMODEL에서 어떻게 모델하면 되나요?
A POR circuit is a small but non-trivial circuit to design in practice. However, its ideal functionality can be modeled using just a few XMODEL primitives as shown below. The first 'slice' primitive detects whether the supply voltage 'Vsup' is higher or lower than the preset threshold 'Vpor'. However, its raw output, labeled as 'a', cannot be the final output of the POR circuit. Assuming an active-low output of the POR circuit named 'RSTb', the 'RSTb' signal must switch to 0 as soon as 'Vsup' falls below 'Vpor', but can switch back to 1 only after 'Vsup' stays above 'Vpor' for the minimum reset period of 'Tpor'.
The following 'transition' primitive and second 'slice' primitive realize this asymmetric behavior. Basically, they model an inertial delay equal to 'Tpor' when propagating the rising edge of 'a' to 'RSTb', but zero delay when propagating the falling edge. The way we model these unequal rising and falling delays is identical to the one explained in this Q&A posting. The 'transition' primitive has its rising transition time set to '2*Tpor' and its falling transition time set to 0. By slicing the resulting output 'b' at its mid-level, we can obtain the desired active-low reset signal 'RSTb'.
The testbench shown below (tb_por1) checks the basic functionality of this POR model, assuming 'Vpor' of 2.0V and 'Tpor' of 100ns. It applies a supply voltage 'Vsup' that gradually increases from 0 to 2.5V and decreases from 2.5V back to 0 using a 'pwl_gen' primitive.
The simulated waveforms are shown below. As expected, the 'RSTb' output transitions from 0 to 1 when 'Vsup' stays above 2.0V for 100ns. On the other hand, 'RSTb' transitions back to 0 as soon as 'Vsup' falls below 2.0V. The waveforms of the signals 'a' and 'b' illustrate the operation of our POR model.
In practice, the design of POR circuit requires high attention to detail, as the circuit must operate robustly even in presence of supply noise. In other words, it must generate a valid reset for the required period when the supply voltage truly rises above the threshold; otherwise, it must not generate a false reset.
To see if our POR model still operates correctly in presence of supply noise, the testbench shown below (tb_por2) adds a 10MHz, 0.1V sinusoidal disturbance to the previous 'Vsup' waveform.
The simulated waveforms of the POR model in this case are shown below. Despite the presence of additional disturbance causing the instantaneous value of 'Vsup' to cross the threshold level multiple times, our POR model does not produce any glitches and de-asserts 'RSTb' only when 'Vsup' stays above 'Vpor' for the period of 'Tpor'.
Attachment: por_20220223.tar.gz
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