Application Notes
XMODEL in the Literature
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Charles Dancak, “A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator”, Design and Verification Conference and Exhibition (DVCon) US, 2024.
(paper, presentation, video & package)
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Seungah Park, et al., “System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog”, Design and Verification Conference and Exhibition (DVCon) Europe, 2023.
(paper & presentation)
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Jaeha Kim, “A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers”, Design and Verification Conference and Exhibition (DVCon) US, 2023.
(paper, presentation, video & package)
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Daniel Stanley, et al., “Fast Validation of Mixed-Signal SoCs”, IEEE Open Journal of the Solid-State Circuits Society, 2021.
(link)
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Chan-Young Park and Jaeha Kim, “A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers”, Design and Verification Conference and Exhibition (DVCon) US, 2021.
(link)
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Seyoung Kim and Jaeha Kim, “An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog”, Design and Verification Conference and Exhibition (DVCon) US, 2021.
(link)
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Chan-Young Park and Jaeha Kim, “Event-Driven Modeling and Simulation of 5G NR-Band RF Transceiver in SystemVerilog,” International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2021.
(link)
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Nayoung Choi and Jaeha Kim, “Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020.
(link)
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Christoph Beyerstedt, et al., “A Fast and Accurate True Event-Driven Phase-Locked Loop Model,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020.
(link)
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Qiwen Liao, et al., “A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS,” IEEE Journal of Solid-State Circuits, 2020.
(link)
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Jieun Jang and Jaeha Kim, “PPV-based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog,” IEEE Transactions on Circuits and Systems I, 2015.
(link)
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Jieun Jang, et al., “PPV-based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog,” IEEE Custom Integrated Circuits Conference (CICC), 2014.
(link)
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Byong Chan Lim, et al., “Digital Analog Design: Enabling Mixed-Signal System Validation,” IEEE Design & Test Magazine, 2014.
(link)
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Jieun Jang, et al., “An Event-Driven Simulation Methodology for Integrated Switching Power Supplies in SystemVerilog,” ACM/IEEE Design Automation Conference (DAC), 2013.
(link)
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Jieun Jang, et al., “Event-Driven Simulation of Volterra Series Models in SystemVerilog,” IEEE Custom Integrated Circuits Conference (CICC), 2013.
(link)
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Jieun Jang, et al., “True Event-Driven Simulation of Analog/Mixed-Signal Behaviors in SystemVerilog: A Decision-Feedback Equalizing (DFE) Receiver Example,” IEEE Custom Integrated Circuits Conference (CICC), 2012.
(link)
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Myeong-Jae Park, et al., “Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation,” IEEE Custom Integrated Circuits Conference (CICC), 2011.
(link)
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Jaeha Kim, et al., “Leveraging Designer’s Intent: A Path Toward Simpler Analog CAD Tools,” IEEE Custom Integrated Circuits Conference (CICC), 2009.
(link)
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