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When simulating an analog-to-digital converter, its multi-bit digital output often contains glitches due to small timing differences in the individual bits' transitions, as shown below.
Is there a way to remove these momentary glitches so we can see the trends in the digital output more clearly? I tried adding an inertial delay, but it didn't work.
Yes, you can use the following code snippet in your SystemVerilog testbench to remove glitches in multi-bit digital bus signals. Here, we assume that Din is a multi-bit digital signal containing momentary glitches. The code produces an output Dout which is free of glitches shorter than 1ns.
// removing glitches in multi-bit bus signals (Din) wire [7:0] Din; reg [7:0] Dout; event Dev; always @(Din) #(1ns) ->Dev; always @(Dev) Dout = Din;
The basic idea is to trigger an event signal Dev with 1ns delay when any bit of Din changes. Because of this 1ns delay, when multiple bits of Din make transitions within the 1ns period, only the last transition event triggers the last always statement, which assigns the final value of Din to Dout. This way, any glitches with durations shorter than 1ns will be removed. Below is the result.
Note that adding an inertial delay of 1ns as shown below can't remove all the glitches, because the inertial delays are applied to the individual bits, not to the overall value expressed by the multi-bit bus signal. In other words, while it can remove glitches occurring in the individual bits (e.g. a signal switching from 8'b10000000 to 8'b00000000 and back to 8'b10000000), it cannot remove glitches occurring in different bits (e.g. a signal switching from 8'b10000000 to 8'b11000000, and then to 8'b01000000).
// this can't remove all the glitches in multi-bit bus signals wire [7:0] Din; wire [7:0] Dout; assign Dout = #(1ns) Din;
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아날로그-디지털 변환기(ADC)를 시뮬레이션하다보면, 아래처럼 복수의 비트로 구성된 디지털 출력에 glitch들이 자주 관찰됩니다. 이는 각 비트가 스위칭하는 시점이 조금씩 달라서 발생하는 일시적인 glitch들입니다.
ADC의 디지털 출력의 변화를 좀더 깨끗하게 관찰하게 위해, 이러한 일시적인 glitch들을 디지털 출력으로부터 제거하는 방법이 있을까요? 디지털 출력에 관성지연(inertial delay)을 추가해보았지만, glitch들이 사라지지 않았습니다.
Yes, you can use the following code snippet in your SystemVerilog testbench to remove glitches in multi-bit digital bus signals. Here, we assume that Din is a multi-bit digital signal containing momentary glitches. The code produces an output Dout which is free of glitches shorter than 1ns.
// removing glitches in multi-bit bus signals (Din) wire [7:0] Din; reg [7:0] Dout; event Dev; always @(Din) #(1ns) ->Dev; always @(Dev) Dout = Din;
The basic idea is to trigger an event signal Dev with 1ns delay when any bit of Din changes. Because of this 1ns delay, when multiple bits of Din make transitions within the 1ns period, only the last transition event triggers the last always statement, which assigns the final value of Din to Dout. This way, any glitches with durations shorter than 1ns will be removed. Below is the result.
Note that adding an inertial delay of 1ns as shown below can't remove all the glitches, because the inertial delays are applied to the individual bits, not to the overall value expressed by the multi-bit bus signal. In other words, while it can remove glitches occurring in the individual bits (e.g. a signal switching from 8'b10000000 to 8'b00000000 and back to 8'b10000000), it cannot remove glitches occurring in different bits (e.g. a signal switching from 8'b10000000 to 8'b11000000, and then to 8'b01000000).
// this can't remove all the glitches in multi-bit bus signals wire [7:0] Din; wire [7:0] Dout; assign Dout = #(1ns) Din;
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