clk_to_delay :
A clock-to-delay domain translator.

The clk_to_delay primitive takes two periodic inputs in and trig and produces an xreal-typed output signal out which expresses the delay of the rising edge of in with respect to the rising edge of trig.

The parameters delay_trig, delay_in, skip_trig, and skip_in control which rising edges of the two inputs are to be compared with. For instance, the parameter delay_trig specifies the initial period during which the input trig’s rising edges are be ignored. Also, the parameter skip_in specifies the number of rising edges of the input in to be ignored after its initial period of delay_in.

For example, if delay_trig, delay_in, skip_trig, and skip_in are set to 1e-6, 2e-6, 5, and 9, respectively, then clk_to_delay starts measuring the delay from the 6th rising edge of trig since 1μsec to the 10th rising edge of in since 2μsec.

Input/Output Terminals

Name	I/O	Type	Description
out	output	xreal	delay output (from trig to in)
in	input	xbit	input pulse
trig	input	xbit	reference trigger pulse

Parameters

Name	Type	Default	Unit	Description
delay_trig	real	0.0	seconds	start delay for ‘trig’
delay_in	real	0.0	seconds	start delay for ‘in’
skip_trig	integer	0	None	number of edges to skip for ‘trig’
skip_in	integer	0	None	number of edges to skip for ‘in’