ADC_DeltaSigmaADCOrder2_CTDSM : A continuous-time delta-sigma modulator (CT-DSM) for a second-order delta-sigma ADC

A second-order continuous-time delta-sigma modulator (CT-DSM) oversamples an analog input and quantizes it into a digital output via noise-shaping, delta-sigma modulation.

This CT-DSM model is composed of two switched-capacitor integrators followed by a clocked comparator, where each switched-capacitor stage is modeled at the circuit level using the switch and capacitor primitives, and ideal OTAs. On the other hand, the clocked comparator is modeled with the compare primitive.

This switched-capacitor CT-DSM model with two non-overlapping clocks: ck1 and ck2. When ck1 rises, the CT-DSM samples the differential analog inputs inp and inn and computes an error compared with the reference level set by the previous Dout value (called “delta”). On the other hand, when ck2 rises, the set of two switched-capacitor integrators accumulates this error (called “sigma”), providing a second-order noise shaping. Finally, the clocked comparator quantizes the noise-shaped signal into a digital output Dout at the next rising edge of ck1. This Dout value is then fed back to the input and determines the reference level to be compared with the sampled input.

Input/Output Terminals

Name	I/O	Type	Description
Dout	output	xbit	digital output
ck1	input	xbit	input clock 1
ck2	input	xbit	input clock 2
cm	input	xreal	common mode
inn	input	xreal	analog input (neg)
inp	input	xreal	analog input (pos)
refn	input	xreal	reference voltage (neg)
refp	input	xreal	reference voltage (pos)

List of Children Cells

BLK_DiffOTAIdeal : An ideal differential operational transconductance amplifier (OTA)