dff_rst_async_xbit :
A D flip-flop with xbit-type input/output’s and asynchronous reset.

The dff_rst_async_xbit primitive models a D flip-flop with a data input d, a clock input clk, an output q, and an asynchronous reset input rst. All the input and output signals are xbit-typed. This primitive is suitable when processing digital signals with precise timing information.

The parameter trig_edge specifies whether the D flip-flop is triggered by the positive edge (+1), negative edge (-1), or both edges (0) of the clock clk. The parameter rst_level specifies whether the reset input rst is active-high (1) or active-low (0). And the parameter init_value defines the initial value of the output q.

The parameter delay_cq defines the propagation delay from the triggering edge of the clock to the output q, and the parameter delay_rq defines the propagation delay from the reset input rst to the output q. These delays are inertial, meaning that if a new input event arrives before the previous change propagates to the output, the output change will be overriden with the one corresponding to the new input event.

When the parameter setup_time or hold_time is specified, the primitive also checks the setup or hold timing constraints, respectively. The parameter setup_time defines the amount of time the input d must be stable before the triggering edge of the clock and the parameter hold_time defines the amount of time the input d must be stable after the triggering edge of the clock. The parameter check_mode defines the action when a timing constraint is violated, whether the primitive changes its output q to a value x (1), displays a warning message (2), or does both (3).

Input/Output Terminals

Name	I/O	Type	Description
q	output	xbit	data output
d	input	xbit	data input
clk	input	xbit	clock input
rst	input	xbit	reset input

Parameters

Name	Type	Default	Unit	Description
trig_edge	integer	1	None	triggering clock edge
rst_level	logic	1’b1	None	active level of reset
init_value	logic	1’bx	None	initial value
delay_cq	real	0.0	seconds	clk-to-q delay
delay_rq	real	0.0	seconds	reset-to-q delay
setup_time	real	`NaN	seconds	setup time constraint
hold_time	real	`NaN	seconds	hold time constraint
check_mode	integer	1	None	action for violation