Well, you can do better with XMODEL! The unique noise frequency transfer characteristic you mentioned is due to the fact that the delay through a clock buffer chain is determined by the integral of the power-supply voltage over the period the clock propagates through the buffer chain. This is nicely summarized in this paper: J. N. Tripathi, V. K. Sharma, and H. Shrimali, "A Review on Power Supply Induced Jitter", IEEE Transactions on Components, Packaging and Manufacturing Technology, March 2019. The so-called "alpha-factor model" describes the variation in the delay of a clock buffer chain (i.e. jitter) using the integration of the relative change in the supply voltage V_DD over the propagation time period, t~t+t_d:

where the scale factor ɑ is defined as the ratio between the relative changes in the delay (t_d) and supply voltage (V_DD):

This integration over a finite time period yields a sinc function in the frequency-domain transfer function, resulting in the notches placed at integer-multiples of the frequency equal to 1/(nominal delay).

As it turns out, the 'delay_to_clk' primitive of XMODEL models this exact same behavior. It delays an xbit-type input 'trig' to an xbit-type output 'out' where the delay amount is determined by the time-average of the input 'in' over the period the xbit signal is propagating through the primitive. Therefore, to model a clock buffer chain with PSIJ, all you have to do is to compute the DC value of the delay from the power-supply voltage and feed it to a 'delay_to_clk' primitive as input.

The package attached to this posting contains a simple example of a clock buffer chain model with the PSIJ effects. The 'sandbox.clkbuf:schematic' cell shown below first computes 'delay' from the supply voltage 'vdd' using an equation: delay=delay0+alpha*(vdd-vdd0), where 'delay0' is the nominal delay of the clock buffer chain at the nominal supply voltage of 'vdd0' and 'alpha' is the sensitivity of the delay with respect to the supply voltage change (please note that it does not have the same definition with the alpha-factor mentioned earlier). The calculated 'delay' is then fed to a 'delay_to_clk' primitive, which delays the input clock 'clk_in' to the output clock 'clk_out'.

Let's measure the PSIJ frequency transfer characteristics of this clock buffer chain model. The 'sandbox.tb_clkbuf:schematic' cell describes a testbench using a 'probe_ac' primitive to sweep the frequency of the sinusoidal change applied to the supply voltage 'vdd' and measure the resulting change in the delay between 'clk_in' and 'clk_out', which is measured by a 'clk_to_delay' primitive. The testbench view 'tb_tfac' sets up the simulation using the 'meas_ac' script. For more details on measuring the AC transfer characteristics using the 'probe_ac' primitive and 'meas_ac' script, please refer to this Q&A link.

Here is the AC transfer function plotted after the simulation. The simulation is run with the following parameter values for the 'clkbuf' model: 'delay0'=10ns, 'vdd0'=1.0, and 'alpha'=10ns/V. As expected, the DC gain between the supply voltage and delay is 10^-8, which is equal to the 'alpha' value of 10ns/V. The AC transfer function follows the shape of a sinc function of which notches are placed at the integer-multiples of 100-MHz, which is equal to the value of 1/'delay0'.

Well, you can do better with XMODEL! The unique noise frequency transfer characteristic you mentioned is due to the fact that the delay through a clock buffer chain is determined by the integral of the power-supply voltage over the period the clock propagates through the buffer chain. This is nicely summarized in this paper: J. N. Tripathi, V. K. Sharma, and H. Shrimali, "A Review on Power Supply Induced Jitter", IEEE Transactions on Components, Packaging and Manufacturing Technology, March 2019. The so-called "alpha-factor model" describes the variation in the delay of a clock buffer chain (i.e. jitter) using the integration of the relative change in the supply voltage V_DD over the propagation time period, t~t+t_d:

where the scale factor ɑ is defined as the ratio between the relative changes in the delay (t_d) and supply voltage (V_DD):

This integration over a finite time period yields a sinc function in the frequency-domain transfer function, resulting in the notches placed at integer-multiples of the frequency equal to 1/(nominal delay).

As it turns out, the 'delay_to_clk' primitive of XMODEL models this exact same behavior. It delays an xbit-type input 'trig' to an xbit-type output 'out' where the delay amount is determined by the time-average of the input 'in' over the period the xbit signal is propagating through the primitive. Therefore, to model a clock buffer chain with PSIJ, all you have to do is to compute the DC value of the delay from the power-supply voltage and feed it to a 'delay_to_clk' primitive as input.

The package attached to this posting contains a simple example of a clock buffer chain model with the PSIJ effects. The 'sandbox.clkbuf:schematic' cell shown below first computes 'delay' from the supply voltage 'vdd' using an equation: delay=delay0+alpha*(vdd-vdd0), where 'delay0' is the nominal delay of the clock buffer chain at the nominal supply voltage of 'vdd0' and 'alpha' is the sensitivity of the delay with respect to the supply voltage change (please note that it does not have the same definition with the alpha-factor mentioned earlier). The calculated 'delay' is then fed to a 'delay_to_clk' primitive, which delays the input clock 'clk_in' to the output clock 'clk_out'.

Let's measure the PSIJ frequency transfer characteristics of this clock buffer chain model. The 'sandbox.tb_clkbuf:schematic' cell describes a testbench using a 'probe_ac' primitive to sweep the frequency of the sinusoidal change applied to the supply voltage 'vdd' and measure the resulting change in the delay between 'clk_in' and 'clk_out', which is measured by a 'clk_to_delay' primitive. The testbench view 'tb_tfac' sets up the simulation using the 'meas_ac' script. For more details on measuring the AC transfer characteristics using the 'probe_ac' primitive and 'meas_ac' script, please refer to this Q&A link.

Here is the AC transfer function plotted after the simulation. The simulation is run with the following parameter values for the 'clkbuf' model: 'delay0'=10ns, 'vdd0'=1.0, and 'alpha'=10ns/V. As expected, the DC gain between the supply voltage and delay is 10^-8, which is equal to the 'alpha' value of 10ns/V. The AC transfer function follows the shape of a sinc function of which notches are placed at the integer-multiples of 100-MHz, which is equal to the value of 1/'delay0'.