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I know SystemVerilog has many object-oriented programming (OOP) features for writing reusable testbenches. Can you show me an example of an OOP-style testbench for analog circuits, where the analog circuits are described in XMODEL?
Sure. There is a great article written by Charles Duncak, titled "SystemVerilog OOP Testbench for Analog Filter: A Tutorial (Part 1)", which showcases an OOP-style SystemVerilog testbench to verify an RC audio bandpass filter, using the XMODEL event-driven verification flow. The article also offers practical coding insights and testbench guidelines, as well as tutorial-level OOP concepts.
You can download its PDF file from this link and download the example package from this link.
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SystemVerilog에는 재활용 가능한 테스트벤치 작성을 위한 객체지향프로그래밍(object-oriented programming; OOP) 기능이 많이 있다고 들었습니다. XMODEL로 기술되어 있는 아날로그 회로에 대한 OOP 스타일의 테스트벤치의 예를 보여주실 수 있나요?
Sure. There is a great article written by Charles Duncak, titled "SystemVerilog OOP Testbench for Analog Filter: A Tutorial (Part 1)", which showcases an OOP-style SystemVerilog testbench to verify an RC audio bandpass filter, using the XMODEL event-driven verification flow. The article also offers practical coding insights and testbench guidelines, as well as tutorial-level OOP concepts.
You can download its PDF file from this link and download the example package from this link.
Please login or Register to submit your answer