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Mapping UDMs in the technology configuration file
I am using the UDM interface of MODELZEN to generate Verilog models from a set of standard logic cells. As the number of logic cells I have is quite large, I find it a bit cumbersome to open the schematic of each cell in Cadence Virtuoso, select all the instances, and define the UDM mapping one-by-one. I wish there is a way to define the UDM mappings in a text form, for instance, within the technology configuration file. Is there such a way?
There are in fact two ways to define UDM mappings in a text form. One way is to write a design information file yourself. All the MODELZEN properties you define in the schematics get extracted into a design information file by GLISTER before the model generation phase, which is a text file in XML format. This file is passed to MODELZEN as one of the input files using the --dbinfo option. This file is named dbinfo_<cellname>.xml and is located in the <MODELZEN_RUNDIR>/netlist/<libname>.<cellname>:<viewname> directory, where <MODELZEN_RUNDIR> is the MODELZEN's run directory (./modelzen.run by default) and <libname>, <cellname>, and <viewname> are the library, cell, and view names of the design cellview, respectively. You can learn its format from a few examples and compose your own design information file. But, writing a design information file by hand is not recommended in general since MODELZEN is not too friendly to possible human mistakes-- MODELZEN assumes the design information files are auto-generated by GLISTER.
The other way is to define the UDM mappings within the technology configuration file using the devo_udmmap dictionary. The example below illustrates how to define devo_udmmap that maps a 2-input NAND gate named 'mynand2' to a UDM 'comblogic' and a D-flipflop named 'mydff' to a UDM 'dflipflop'. You can see how the model mapping (model), port mappings (ports) and option parameter (params) of each UDM mapping are defined in a Python dictionary format. Since the technology configuration file itself is an executable Python script, it is possible to utilize Python functions or expressions to efficiently define UDM mappings for a large set of cells. You can also use wildcards (e.g., wildcard('OUT*')) or regular expressions (e.g., regex(r'[A-Z]')) for the net names. However, a current limitation of this approach is that you can only map a whole cell to a UDM. In other words, you cannot map a part of cell to a UDM using devo_udmmap.
# UDM mapping
devo_udmmap = {
'mynand2' : dict(
model = 'comblogic',
ports = {
'A' : ('in', [1.2]),
'B' : ('in', [1.2]),
'Y' : ('out', [1.2]),
'VDD' : ('vpwr', 1.2),
'VSS' : ('vgnd', 0.0),
},
),
'mydff' : dict(
model = 'dflipflop',
ports = {
'IN' : ('d', [1.2]),
'OUT' : ('q', [1.2]),
'OUT_B' : ('q', [1.2]),
'CLK' : ('ck', [1.2]),
'CLK_B' : ('ckb', [1.2]),
'VDD' : ('vpwr', 1.2),
'VSS' : ('vgnd', 0.0),
},
params = {
'init_value' : '0',
},
),
}
From the XMODEL 2023.09 Release, the 'devo' utility script supports the '--udmmap' option, which can be used to show the examples of mapping UDMs in the technology configuration file. This can alleviate the need for memorizing the names and types of the ports and parameters supported by each UDM.
The basic usage of the 'devo' utility with the '--udmmap' option is as follows. Simply provide a list of UDM names for which you'd like to see the mapping examples:
$ devo --udmmap <UDM_NAME1> <UDM_NAME2> ...
Here is an example of running the utility for the 'amp_linear' UDM:
$ devo --udmmap amp_linear
# UDM mapping
devo_udmmap = {
'CELLNAME0' : dict(
model = 'amp_linear',
ports = {
'PORT_VIN' : ('vin', 0.0), # Vin Bias (type: real)
'PORT_IIN' : ('iin', 0.0), # Iin Bias (type: real)
'PORT_VOUT' : ('vout', 0.0), # Iout Bias (type: real)
'PORT_IOUT' : ('iout', 0.0), # Vout Bias (type: real)
'PORT_MODE' : ('mode', [1.0]), # Level (type: modespec)
'PORT_VPWR' : ('vpwr', 1.0), # Value (type: real)
'PORT_VGND' : ('vgnd', 0.0), # Value (type: real)
'PORT_VBIAS' : ('vbias', 0.0), # Value (type: real)
'PORT_IBIAS' : ('ibias', 0.0), # Value (type: real)
},
params = {
'rth' : 1000000.0, # Resistance Threshold for Open Circuits (type: real)
'cth' : 1e-15, # Capacitance Threshold for Open Circuits (type: real)
'fc' : 1000000.0, # Capacitance Measurement Frequency (type: real)
'gmth' : 1e-06, # Transconductance Threshold (type: real)
'num_thread' : 1, # No. of Parallel Threads (type: int)
'tgrace_mode' : 1e-09, # Grace Period for Invalid 'mode' (type: real)
},
),
}
Note that this is only an example. You will need to modify the cell or subcircuit name to which you are mapping the UDM and edit the list of port mappings and parameter values.
If you'd like to see the examples of all the UDMs available, you can use a special keyword 'all':
$ devo --udmmap all
If you don't specify the UDM names, the utility displays the list of available UDMs.
$ devo --udmmap
*** WARNING: No UDM model names are specified. The available UDMs are:
amp_linear
capacitor
comblogic
delayline
dflipflop
dlatch
filter
inductor
poly_func
pwl_func
refgen
resistor
select
slice
srlatch
switch
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Technology configuration 파일에서 UDM 매핑 정의하는 방법
MODELZEN의 UDM 인터페이스를 사용해서 스탠다드 로직셀로부터 Verilog 모델을 추출하고 있습니다. 로직셀의 숫자가 많아질수록, 각 셀의 스키매틱을 하나하나씩 Cadence Virtuoso에서 열어서, 그 안의 모든 instance를 선택하 UDM 매핑을 정의하는 일이 단순 노동이 되고 있습니다. GUI 환경 대신 텍스트 파일로 UDM 매핑을 정의할 수 있으면 좀더 편리하지 않을까 생각이 됩니다. 예를 들면, technology configuration 파일내에서 UDM 매핑을 정의하는 방법이 있을까요?
There are in fact two ways to define UDM mappings in a text form. One way is to write a design information file yourself. All the MODELZEN properties you define in the schematics get extracted into a design information file by GLISTER before the model generation phase, which is a text file in XML format. This file is passed to MODELZEN as one of the input files using the --dbinfo option. This file is named dbinfo_<cellname>.xml and is located in the <MODELZEN_RUNDIR>/netlist/<libname>.<cellname>:<viewname> directory, where <MODELZEN_RUNDIR> is the MODELZEN's run directory (./modelzen.run by default) and <libname>, <cellname>, and <viewname> are the library, cell, and view names of the design cellview, respectively. You can learn its format from a few examples and compose your own design information file. But, writing a design information file by hand is not recommended in general since MODELZEN is not too friendly to possible human mistakes-- MODELZEN assumes the design information files are auto-generated by GLISTER.
The other way is to define the UDM mappings within the technology configuration file using the devo_udmmap dictionary. The example below illustrates how to define devo_udmmap that maps a 2-input NAND gate named 'mynand2' to a UDM 'comblogic' and a D-flipflop named 'mydff' to a UDM 'dflipflop'. You can see how the model mapping (model), port mappings (ports) and option parameter (params) of each UDM mapping are defined in a Python dictionary format. Since the technology configuration file itself is an executable Python script, it is possible to utilize Python functions or expressions to efficiently define UDM mappings for a large set of cells. You can also use wildcards (e.g., wildcard('OUT*')) or regular expressions (e.g., regex(r'[A-Z]')) for the net names. However, a current limitation of this approach is that you can only map a whole cell to a UDM. In other words, you cannot map a part of cell to a UDM using devo_udmmap.
# UDM mapping
devo_udmmap = {
'mynand2' : dict(
model = 'comblogic',
ports = {
'A' : ('in', [1.2]),
'B' : ('in', [1.2]),
'Y' : ('out', [1.2]),
'VDD' : ('vpwr', 1.2),
'VSS' : ('vgnd', 0.0),
},
),
'mydff' : dict(
model = 'dflipflop',
ports = {
'IN' : ('d', [1.2]),
'OUT' : ('q', [1.2]),
'OUT_B' : ('q', [1.2]),
'CLK' : ('ck', [1.2]),
'CLK_B' : ('ckb', [1.2]),
'VDD' : ('vpwr', 1.2),
'VSS' : ('vgnd', 0.0),
},
params = {
'init_value' : '0',
},
),
}
From the XMODEL 2023.09 Release, the 'devo' utility script supports the '--udmmap' option, which can be used to show the examples of mapping UDMs in the technology configuration file. This can alleviate the need for memorizing the names and types of the ports and parameters supported by each UDM.
The basic usage of the 'devo' utility with the '--udmmap' option is as follows. Simply provide a list of UDM names for which you'd like to see the mapping examples:
$ devo --udmmap <UDM_NAME1> <UDM_NAME2> ...
Here is an example of running the utility for the 'amp_linear' UDM:
$ devo --udmmap amp_linear
# UDM mapping
devo_udmmap = {
'CELLNAME0' : dict(
model = 'amp_linear',
ports = {
'PORT_VIN' : ('vin', 0.0), # Vin Bias (type: real)
'PORT_IIN' : ('iin', 0.0), # Iin Bias (type: real)
'PORT_VOUT' : ('vout', 0.0), # Iout Bias (type: real)
'PORT_IOUT' : ('iout', 0.0), # Vout Bias (type: real)
'PORT_MODE' : ('mode', [1.0]), # Level (type: modespec)
'PORT_VPWR' : ('vpwr', 1.0), # Value (type: real)
'PORT_VGND' : ('vgnd', 0.0), # Value (type: real)
'PORT_VBIAS' : ('vbias', 0.0), # Value (type: real)
'PORT_IBIAS' : ('ibias', 0.0), # Value (type: real)
},
params = {
'rth' : 1000000.0, # Resistance Threshold for Open Circuits (type: real)
'cth' : 1e-15, # Capacitance Threshold for Open Circuits (type: real)
'fc' : 1000000.0, # Capacitance Measurement Frequency (type: real)
'gmth' : 1e-06, # Transconductance Threshold (type: real)
'num_thread' : 1, # No. of Parallel Threads (type: int)
'tgrace_mode' : 1e-09, # Grace Period for Invalid 'mode' (type: real)
},
),
}
Note that this is only an example. You will need to modify the cell or subcircuit name to which you are mapping the UDM and edit the list of port mappings and parameter values.
If you'd like to see the examples of all the UDMs available, you can use a special keyword 'all':
$ devo --udmmap all
If you don't specify the UDM names, the utility displays the list of available UDMs.
$ devo --udmmap
*** WARNING: No UDM model names are specified. The available UDMs are:
amp_linear
capacitor
comblogic
delayline
dflipflop
dlatch
filter
inductor
poly_func
pwl_func
refgen
resistor
select
slice
srlatch
switch
Please login or Register to submit your answer