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Why MODELZEN declares the model’s ports with macros like `input_xreal or `output_xreal?
I noticed that MODELZEN generates a model that declares the module ports using macros like `input_xreal or `output_xreal. See an example below. What are the definitions of these macros? Can I generate models without those macros?
The port macros you noticed are defined in the $XMODEL_HOME/include/xmodel.h header file as listed below:
As you can see, the definitions of these port macros are almost identical to their names. In fact, you can generate models without these port macros by setting the devo_options['use_portmacros'] option to False in the technology configuration file (the tech_config.py file):
devo_options['use_portmacros'] = False
You may wonder why these port macros are used in the first place. MODELZEN inserts these port macros in case you may want to use the models for purposes other than simulations by applying different definitions to them. One example is a place-and-route tool, which does not run any simulations with Verilog models, but reads the connectivity information described by the Verilog models. In this case, you may want models that define all the input/output ports as plain wire-type ports. With the models using these port macros for the module ports, you can simply apply a new header file that defines all the port macros as the wire-type ports, without having to modify the models.
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왜 MODELZEN은 모델의 포트들을`input_xreal이나 `output_xreal같은 매크로로 선언하나요?
MODELZEN이 모델을 생성할때 모듈의 입출력 포트들을 `input_xreal이나 `output_xreal 같은 매크로를 사용해 선언하는 것을 보았습니다. 아래의 예제를 참고하세요. 이 매크로들의 정의는 무엇입니까? 이 매크로들 없이 모델을 생성할 수도 있나요?
The port macros you noticed are defined in the $XMODEL_HOME/include/xmodel.h header file as listed below:
As you can see, the definitions of these port macros are almost identical to their names. In fact, you can generate models without these port macros by setting the devo_options['use_portmacros'] option to False in the technology configuration file (the tech_config.py file):
devo_options['use_portmacros'] = False
You may wonder why these port macros are used in the first place. MODELZEN inserts these port macros in case you may want to use the models for purposes other than simulations by applying different definitions to them. One example is a place-and-route tool, which does not run any simulations with Verilog models, but reads the connectivity information described by the Verilog models. In this case, you may want models that define all the input/output ports as plain wire-type ports. With the models using these port macros for the module ports, you can simply apply a new header file that defines all the port macros as the wire-type ports, without having to modify the models.
Please login or Register to submit your answer