Don’t worry – it is the correct behavior of MODELZEN. MODELZEN may change the directions of the ports when generating models so that the generated models would simulate in SystemVerilog without errors. In other words, your inverter model will correctly produce the output waveform responding to the input.

XMODEL has a unique capability of simulating circuit-level models (CLMs) within SystemVerilog, while SystemVerilog itself only supports the simulation of block-level models. In circuit-level models, their node voltages and branch currents are governed by circuit equations and must be solved simultaneously accounting for their bidirectional interactions. In block-level models, the output of each block or module is determined by its inputs only. This is basically why shorting two output ports in SystemVerilog gives an error. There can be only one driver for a given signal, particularly for so-called “variable-type” signals like xreal and xbit.

Defining the ports of the circuit-level models (i.e. the models made of circuit primitives such as nmosfet and pmosfet) as inputs is a way of avoiding this multiple-driver error in SystemVerilog. In other words, SystemVerilog won’t complain even when you take two of these inverters and short their inputs and outputs together to increase the drive strength.

This is also the reason why all the ports of the XMODEL’s circuit primitives are defined as inputs. Yet, the XMODEL simulation engine treats all their ports as bidirectional ports and computes their voltages and currents via its efficient, event-driven algorithm.

It is noteworthy that MODELZEN doesn’t just turn all the ports into input ports. It knows when it must use output ports, for example, when the generated models contain function primitives such as buffer or connect primitives such as xreal_to_bit. The default behavior of MODELZEN is to ignore the port directions described in the source schematics and determine the proper port directions itself based on the types of primitives connected to each port. You can disable this behavior by the setting the ‘ignore_pindir’ option to False in the technology configuration file as shown below:

devo_options['ignore_pindir'] = False

But doing so is not recommended in general as you may encounter various errors and issues due to the conflicts in port directions.

Don’t worry – it is the correct behavior of MODELZEN. MODELZEN may change the directions of the ports when generating models so that the generated models would simulate in SystemVerilog without errors. In other words, your inverter model will correctly produce the output waveform responding to the input.

XMODEL has a unique capability of simulating circuit-level models (CLMs) within SystemVerilog, while SystemVerilog itself only supports the simulation of block-level models. In circuit-level models, their node voltages and branch currents are governed by circuit equations and must be solved simultaneously accounting for their bidirectional interactions. In block-level models, the output of each block or module is determined by its inputs only. This is basically why shorting two output ports in SystemVerilog gives an error. There can be only one driver for a given signal, particularly for so-called “variable-type” signals like xreal and xbit.

Defining the ports of the circuit-level models (i.e. the models made of circuit primitives such as nmosfet and pmosfet) as inputs is a way of avoiding this multiple-driver error in SystemVerilog. In other words, SystemVerilog won’t complain even when you take two of these inverters and short their inputs and outputs together to increase the drive strength.

This is also the reason why all the ports of the XMODEL’s circuit primitives are defined as inputs. Yet, the XMODEL simulation engine treats all their ports as bidirectional ports and computes their voltages and currents via its efficient, event-driven algorithm.

It is noteworthy that MODELZEN doesn’t just turn all the ports into input ports. It knows when it must use output ports, for example, when the generated models contain function primitives such as buffer or connect primitives such as xreal_to_bit. The default behavior of MODELZEN is to ignore the port directions described in the source schematics and determine the proper port directions itself based on the types of primitives connected to each port. You can disable this behavior by the setting the ‘ignore_pindir’ option to False in the technology configuration file as shown below:

devo_options['ignore_pindir'] = False

But doing so is not recommended in general as you may encounter various errors and issues due to the conflicts in port directions.