xbit type in XMODEL

The xbit type in XMODEL is introduced to express digital signals with accurate timing information without being limited by the simulation time step in SystemVerilog. Note that in SystemVerilog, time can only be expressed as an integer multiple of a chosen simulation time step, called time precision. Hence, the resolution in expressing the timing of digital signals using the standard Verilog types such as wire and reg cannot be finer than this simulation time step.
The xbit type overcomes this limitation by bundling a time offset variable along with the signal value. This time offset variable takes a double-precision floating-point value, providing a virtually infinite resolution in expressing the signal’s timing. The following figure compares the clock waveforms expressed in the wire/reg type and in the xbit type. In general, a clock signal may not have its transitions perfectly aligned with the time steps of SystemVerilog. While this misalignment would introduce quantization errors in timing when the signal is expressed with the wire/reg type, it would not with the xbit type, since the quantization errors would be stored in their time offset variables. For instance, when an xbit-type signal switches at time 10 and its time offset value is -0.6, it implies that the actual transition has occurred at time 9.4.

Hence, the xbit type is suitable for expressing timing-critical signals such as clocks and timing pulses, of which frequency, period, delay, or pulse width must be precisely expressed. The examples include the clocks produced by phase-locked loops or delay-locked loops, and the pulses switching the DC-DC converter stages.
Nonetheless, we do not recommend using the xbit types for all digital signals. In fact, for most digital circuits, describing them in standard Verilog with wire/reg-type signals can be the better choice. It is because in most digital circuits, it is not necessary to preserve the precise timing information of digital signals, as long as the signals meet the maximum and minimum timing constraints. It is more advantageous to describe those digital circuits in standard Verilog, as it enables the faster speed of simulation and also keeps the design synthesizable.
The programmable frequency divider example shown below illustrates the usage of the xbit type and wire/reg type. This circuit is used as part of a phase-locked loop, hence its output timing must be accurately determined by the input timing. However, the value which the output signal switches to is determined by a digital finite-state machine composed of a programmable counter and a delta-sigma modulator (DSM). Therefore, it is desirable to describe the programmable counter and DSM in standard Verilog only using wire/reg type signals, while describing the final retiming flip-flop with a 'dff_xbit' primitive producing an xbit-type output clock from an xbit-type input clock. This way, we have a timing-accurate model for the frequency divider while keeping the description for the digital parts synthesizable. This model would also run faster than the model using xbit types for all the signals.