From this link, you can download the package of a simple continuous-time delta-sigma ADC model. The ADC consists largely of a delta-sigma modulator (DSM) and a digital decimation filter.

The cellview ctdsm.ctdsm:schematic shown below models a second-order DSM with switched-capacitor integrators followed by a clocked comparator, where the switched-capacitor integrators are modeled directly using the XMODEL circuit-level primitives corresponding to switches, capacitors, and ideal OTAs. The clocked comparator is modeled using the ‘compare’ primitive. The clock signals (ck1 and ck2) are in xbit types while the other signals are in xreal types.

Cellview ctdsm.ctdsm:schematic

The cellview ctdsm.tb_ctdsm:schematic is a testbench schematic for simulating the described DSM along with a digital decimation filter. The decimation filter is described in pure Verilog, so it can be synthesized into an implementation. The testbench feeds a 1MHz sinusoidal input to the DSM, which oversamples the input at a 1GHz frequency and produces a 1-bit stream output (Dout). The subsequent decimation filter converts this 1-bit stream input to a 21-bit stream output (out) with a decimation factor of 16.

Testbench ctdsm.tb_ctdsm:schematic

The final output waveform of a 5-us simulation is shown below. The simulation takes only 10 seconds thanks to the XMODEL’s event-driven algorithm that can simulate the analog circuits in SystemVerilog.

From this link, you can download the package of a simple continuous-time delta-sigma ADC model. The ADC consists largely of a delta-sigma modulator (DSM) and a digital decimation filter.

The cellview ctdsm.ctdsm:schematic shown below models a second-order DSM with switched-capacitor integrators followed by a clocked comparator, where the switched-capacitor integrators are modeled directly using the XMODEL circuit-level primitives corresponding to switches, capacitors, and ideal OTAs. The clocked comparator is modeled using the ‘compare’ primitive. The clock signals (ck1 and ck2) are in xbit types while the other signals are in xreal types.

Cellview ctdsm.ctdsm:schematic

The cellview ctdsm.tb_ctdsm:schematic is a testbench schematic for simulating the described DSM along with a digital decimation filter. The decimation filter is described in pure Verilog, so it can be synthesized into an implementation. The testbench feeds a 1MHz sinusoidal input to the DSM, which oversamples the input at a 1GHz frequency and produces a 1-bit stream output (Dout). The subsequent decimation filter converts this 1-bit stream input to a 21-bit stream output (out) with a decimation factor of 16.

Testbench ctdsm.tb_ctdsm:schematic

The final output waveform of a 5-us simulation is shown below. The simulation takes only 10 seconds thanks to the XMODEL’s event-driven algorithm that can simulate the analog circuits in SystemVerilog.