Composing an XMODEL testbench that replays the SPICE-simulated waveforms using a ‘replay_all’ primitive.

Yes, there is! In fact, there are more than one ways to compose an XMODEL testbench that supplies the same input stimuli with the SPICE testbench. Here I will introduce a way to use a 'replay_all' primitive in GLISTER.

This 'replay_all' primitive basically replays all the signals stored in an FSDB waveform file with a specified hierarchy level. It is a pseudo-primitive that exists only as a symbol and GLISTER netlists it to a collection of 'replay_xbit' or 'replay_xreal' primitives depending on each signal's type. Please refer to XMODEL Reference Manual for more details on the 'replay_xbit' and 'replay_xreal' primitives.

With the 'replay_all' primitive, it is easy to build an XMODEL testbench that replays the stimulus signals used in the SPICE simulation and supplies them to the model. If you replay the circuit's responses as well, you can easily compare them with the model's responses and check the circuit vs. model equivalence.

For an illustration, let's assume that we have run a SPICE simulation on a circuit called 'ctle_adapt' of which schematic is shown below and stored its input and output waveforms in an FSDB-format file named 'waves.fsdb'. Note that most SPICE simulators including HSPICE and Spectre support FSDB as one of its output waveform file formats. For instance, for HSPICE, you can add the following option statement in its input file:

.OPTION FSDB

and for Spectre, you can add:

settings options rawfmt=fsdb

to store the simulated waveforms in an FSDB format. You can also set the equivalent options from the Cadence ADE menus.

You can check the signals and their names stored in the FSDB waveform file by executing XWAVE with the '-l' option. In our example, the following command yields:

$ xwave -l waves.fsdb

----------------------------------------------------------------------------------------------------------------
Filename:
    waves.fsdb

Attributes:
    date         : unknown
    timestep     : 1e-15
    scopesep     : .
    timescale    : 1e-15
    simulator    : unknown

Variables:
    Cctrl\<0\>  type:real
    Cctrl\<1\>  type:real
    Cctrl\<2\>  type:real
    Cctrl\<3\>  type:real
    Rctrl\<0\>  type:real
    Rctrl\<1\>  type:real
    Rctrl\<2\>  type:real
    Rctrl\<3\>  type:real
    bias        type:real
    inn         type:real
    inp         type:real
    outn        type:real
    outp        type:real
    vdd         type:real

----------------------------------------------------------------------------------------------------------------

If XWAVE cannot read your FSDB waveform file, it is possible that it failed locating the FSDB reader library. For more information, please refer to this link (https://www.scianalog.com/support/community/question/1550/).

As mentioned earlier, the 'replay_all' primitive is useful in composing a schematic testbench that replays the waveforms stored in an FSDB waveform file. In the schematic testbench shown below named 'tb_replay', an instance of the 'ctle_adapt' model is added first as a "model-under-test". A tip: when you select an instance and press the space bar, Cadence Virtuoso automatically creates the wire stubs and labels connected to the instance terminals.

Now, it's time to add the 'replay_all' primitive. Open the 'Add Instance' dialog, select 'replay_all' symbol from the 'xmodel_prims' library, and define the name of the FSDB waveform file and the desired hierarchy prefix of the signals to be replayed. For instance, if you want to replay the signals located at A1.B2.C3, define "A1.B2.C3" as the hierarchy prefix. For top-level signals, you may leave the hierarchy prefix as blank. For the rest of the options, you may refer to the documentations on the replay_xreal/xbit primitives.

Once you enter the waveform filename and hierarchy prefix correctly, you will notice that the signals to be replayed will appear as the terminals of the 'replay_all' symbol. Place this symbol on the testbench schematic. Again, you can press the space bar to create the wire stubs and labels.

Now, add a 'dump' primitive and you are almost done! In case you are replaying the output waveforms of the SPICE simulation as well (e.g. outp and outn in this example), you need to modify their names (e.g. outp_SPICE and outn_SPICE) so that you can compare them without the name collisions. Also, in case the signal names stored in the FSDB waveform file are different from the ones used in the testbench schematic, you may need to modify some of the auto-generated names to establish connections.

It is possible that there is a type mismatch between a signal stored on the waveform file and a terminal port of the model. For instance, one can be a digital type (e.g. xbit, wire, or reg) while the other is an analog type (e.g. xreal or real). In this case, GLISTER needs to know the conversion level information in order to insert the connectors in-between. For instance, typing the following line in the CIW defines the logic-1 level globally at 1.2V:

xmodelConvLevel1 = 1.2

There are also ways to set different conversion levels for individual connections. For more information, please refer to the section on "Automatic Type Detection and Coercion" in the GLISTER User Guide.

Once your testbench schematic is ready, you can netlist it and run the XMODEL simulation. You can examine the responses of the model to the stimuli and even compare them with those of the circuit. For example, in the waveforms shown below, the ones on the top are the output waveforms of the model while the ones on the bottom are those of the circuit.